FROM GCC 3.4 MANUAL
3.17.11 Intel 386 and AMD x86-64 Options
These `-m’ options are defined for the i386 and x86-64 family of
computers:
`-mtune=CPU-TYPE’
Tune to CPU-TYPE everything applicable about the generated code,
except for the ABI and the set of available instructions. The
choices for CPU-TYPE are:
i386
Original Intel’s i386 CPU.
_i486_
Intel's i486 CPU. (No scheduling is implemented for this
chip.)
_i586, pentium_
Intel Pentium CPU with no MMX support.
_pentium-mmx_
Intel PentiumMMX CPU based on Pentium core with MMX
instruction set support.
i686, pentiumpro
Intel PentiumPro CPU.
_pentium2_
Intel Pentium2 CPU based on PentiumPro core with MMX
instruction set support.
_pentium3, pentium3m_
Intel Pentium3 CPU based on PentiumPro core with MMX and SSE
instruction set support.
_pentium-m_
Low power version of Intel Pentium3 CPU with MMX, SSE and
SSE2 instruction set support. Used by Centrino notebooks.
_pentium4, pentium4m_
Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set
support.
_prescott_
Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2
and SSE3 instruction set support.
_nocona_
Improved version of Intel Pentium4 CPU with 64-bit
extensions, MMX, SSE, SSE2 and SSE3 instruction set support.
_k6_
AMD K6 CPU with MMX instruction set support.
_k6-2, k6-3_
Improved versions of AMD K6 CPU with MMX and 3dNOW!
instruction set support.
_athlon, athlon-tbird_
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE
prefetch instructions support.
_athlon-4, athlon-xp, athlon-mp_
Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and
full SSE instruction set support.
_k8, opteron, athlon64, athlon-fx_
AMD K8 core based CPUs with x86-64 instruction set support.
(This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and
64-bit instruction set extensions.)
_winchip-c6_
IDT Winchip C6 CPU, dealt in same way as i486 with additional
MMX instruction set support.
_winchip2_
IDT Winchip2 CPU, dealt in same way as i486 with additional
MMX and 3dNOW! instruction set support.
_c3_
Via C3 CPU with MMX and 3dNOW! instruction set support. (No
scheduling is implemented for this chip.)
_c3-2_
Via C3-2 CPU with MMX and SSE instruction set support. (No
scheduling is implemented for this chip.)
While picking a specific CPU-TYPE will schedule things
appropriately for that particular chip, the compiler will not
generate any code that does not run on the i386 without the
`-march=CPU-TYPE' option being used.
(edit)
un lien